In the chipset design concept, a computing system may include a set of related functional chips that are designed and produced to be used together. In contrast, chipset technology has recently progressed toward a system-on-chip (SOC) concept in which various functional blocks, previously provided on related individual chips, are integrated onto a single semiconductor chip.
The SOC concept integrates various functional block cores such as, for example, a microprocessor, an on-chip memory, an audio controller, a video controller, a coder and decoder (codec), and/or a digital signal processor (DSP), on a single chip, thereby potentially reducing the total product size, time, and/or cost required for developing a system including the functional block cores.
A functional block core used in an SOC system can be developed independently or can be provided by a core that has been already developed. This reusability of functional block cores may save development time and/or cost.
For data-intensive applications such as the processing of broadband video and/or audio, it may be desirable to provide a large bandwidth for data communication between some of the functional block cores. Accordingly, the expected data traffic load between functional block cores may increase.
For example, in the case of an SOC system in which a large-capacity on-chip memory or a controller (or codec) for processing audio/video signals is built, a large development effort may be required to enable a sufficient level of data communication between functional block cores.
Generally, a bus is used for transferring data between many chips. For example, in an embedded system using an Advanced RISC Machine (ARM) CPU, functional units such as a CPU, a memory controller, and/or a display controller may be connected by a bus architecture such as an Advanced Microcontroller Bus Architecture (AMBA).
In some cases, the functional block cores in an SOC system may be connected by the AMBA bus architecture. For example, in the case of a conventional low-integrated SOC system, a chip-level bus architecture may be used without significant alteration.
However, in a highly integrated SOC system, the width of wires in the system bus may be narrowed. Accordingly, the inductance, resistance and capacitance of the bus wires may be increased in comparison with the size of gates in the functional block core. Consequently, when a conventional bus architecture is used in a highly integrated SOC system, it may be difficult to achieve a desired level of system performance.
Accordingly, interest has developed in a Network-On-Chip (NOC) concept including an efficient on-chip bus architecture corresponding to the SOC concept and associated design methodology. Various on-chip bus architectures have recently been proposed.
A conventional on-chip bus architecture 100 is illustrated in FIG. 1. The architecture 100 is a type of bus architecture usable in an SOC architecture including nine functional block cores 110a-110i, and is a slight modification of a bus structure disclosed in U.S. Pat. No. 5,974,487.
Referring to FIG. 1, a conventional on-chip bus architecture 100 includes nine functional block cores 110a-110i configured to perform various functions, switch points 120a-120l operable to mediate (or relay) data communication between the functional blocks cores 110a-110i, and inter-switch links 130a-130l and 131a-131h interconnecting the switch points 120a-120l. 
The inter-switch links 130a-130l, 131a-131h and the switch points 120a-120l are configured in a two-dimensional mesh 140 of rings within the overall bus architecture 100.
The switch points 120a-120l are positioned at interconnections of the mesh 140. Each of the switch points 120a-120l receives data from a source switch point through an inter-switch link and transfers the received data to a destination switch point through an appropriate inter-switch link.
Further, each of the switch points 120a-120l may receive data from a source switch point through an inter-switch link and then transfer the received data to a functional block core connected thereto. Each switch point may receive data from a connected functional block core and transfer the received data to a destination functional block core through a corresponding inter-switch link via an appropriate switch point.
Each of the inter-switch links 130a-130l, 131a-131i may be a bi-directional link or a unidirectional link. A bi-directional link may include a pair of uni-directional wires having opposite communication directions or, alternatively, one bi-directional wire.
In the above-described on-chip bus architecture 100, when the functional block core 110a needs to transfer data to the functional block core 110e, the functional block core 110a transfers the data to the switch point 120a connected thereto.
The switch point 120a receives the data from the functional block core 110a and transfers the received data to the switch point 120d through the inter-switch link 131a connected between the switch points 120a and 120d. The switch point 120d receives the data from the switch point 120a through the inter-switch link 131a and finally transfers the received data to the functional block core 110e connected thereto.
That is, in the on-chip bus architecture 100, data communication between functional block cores 110a-110i is performed through the switch points connected respectively to the functional block cores 110a-110i and inter-switch links 130a-130l, 131a-131h that connect the switch points 120a-120l. 
FIG. 2 is a block diagram of a conventional switch point 200 used in the mesh-based on-chip bus architecture 100, which is disclosed in “A Network on Chip Architecture and Design Methodology”, Proc. ISVLSI 02, April 2002.
Referring to FIG. 2, a conventional switch point 200 includes a plurality of switch ports 220a-220d, which include incoming links 213a-213d, outgoing links 214a-214d, queues 210a-210d for queuing data received through the incoming links 213a-213d, multiplexers (MUXs) 211a-211d for outputting received data over a selected outgoing link 214a-214d, and selection logic units 212a-212d for controlling the multiplexers 211a-211d. 
The incoming links 213a-213d and outgoing links 214a-214d together make up bi-directional inter-switch links. That is, the bi-directional inter-switch links include the incoming links 213a-213d for receiving data into the switch point 200 from the outside and the outgoing links 214a-214d for transferring data from the switch point 200 to the outside.
As illustrated in FIG. 1, the switch points 120a-120l are positioned at the interconnection points of the mesh 140. Each of the switch points 120d, 120e, 120h and 120i is connected to four inter-switch links, respectively, while each of the switch points 120a, 120b, 120c, 120f, 120g, 120j, 120k and 1201 is connected to three inter-switch links, respectively.
Referring again to FIG. 2, the switch point 200 has a structure corresponding to one of the switch points 120d, 120e, 120h and 120i, each of which is connected to four inter-switch links. In particular, the switch point 200 has a structure corresponding to one of the switch points 120h and 120i, whose left lower end is connected to a functional block core 110g, 110h. 
Data received from another switch point through one of the incoming links 213a-213d is inputted to one of the queues 210a-210d, and data outputted from the queue 210a-210d is selected by at least one of the remaining switch ports 220a-220d and is outputted via an outgoing line 214a-214d. In order to perform this mediation function, each switch port 220a-220d of the switch point 200 is provided with a multiplexer 211a-211d for selecting one of the incoming data queues 210a-210d which receives data from the other switch points, and outputs data through an associated inter-switch link.
For example, in order to determine data to be outputted through the outgoing inter-switch link 214d, the multiplexer 211d selects data that is received through one of the remaining three inter-switch links 213a-213c and is queued in one of the queues 210a-210c. The multiplexer 211d is controlled by the selection logic unit 212d. 
The switch point 200 further includes a bus interface port 220e connected to an interface of a functional block core (not shown) connected thereto.
The bus interface port 220e includes a queue 210e for queuing data received from the connected functional block core, a multiplexer 211e for selectively transmitting data from the inter-switch links 213a-213d to the functional block core, and a selection logic unit 212e for controlling the multiplexer 211e. 
The on-chip bus architecture 100 using the switch point 200 may be advantageous in that it may be modular and easy to extend, and may have a short link length.
However, the on-chip bus architecture 100 may be disadvantageous in that the on-chip bus architecture 100 may have to use an inter-switch link even for data communication between the functional block cores positioned close to each other.
Accordingly, the power consumption and communication delay of the on-chip bus architecture 100 may undesirably increase in proportion to the number of inter-switch links used in the bus architecture 100.